Role Overview
As a Staff/Sr. Staff/Principal STA/Synthesis Engineer at Velaura AI, you will own RTL-to-gate synthesis, static timing analysis, and timing closure for next-generation AI and high-performance computing silicon. You will be responsible for driving implementation quality, timing convergence, power optimization, and sign-off readiness
for complex compute, CPU, VPU, and low-power cores targeting advanced process technologies. You will work closely with RTL, architecture, DFT, physical design, CAD, verification, and product engineering teams to achieve aggressive Performance, Power, Area, and Cost targets. This is a highly visible technical role where you will influence
synthesis strategy, timing closure methodology, constraint quality, ECO flows, and implementation best practices for complex ASIC/SoC designs.
Role Overview
As a Staff/Sr. Staff/Principal STA/Synthesis Engineer at Velaura AI, you will own RTL-to-gate synthesis, static timing analysis, and timing closure for next-generation AI and high-performance computing silicon. You will be responsible for driving implementation quality, timing convergence, power optimization, and sign-off readiness
for complex compute, CPU, VPU, and low-power cores targeting advanced process technologies. You will work closely with RTL, architecture, DFT, physical design, CAD, verification, and product engineering teams to achieve aggressive Performance, Power, Area, and Cost targets. This is a highly visible technical role where you will influence
synthesis strategy, timing closure methodology, constraint quality, ECO flows, and implementation best practices for complex ASIC/SoC designs.