Role Overview
As a Staff/Sr. Staff Physical Verification Engineer at Velaura AI, you will own block-level and full-chip physical verification and signoff for next-generation AI and high-performance computing silicon. You will drive physical verification from block-level implementation through full-chip integration and final tape-out, working on complex SoC designs targeting advanced process technologies.
This is a highly hands-on technical role requiring deep expertise in DRC, LVS, ERC, PERC, antenna, ESD/EOS, and reliability verification, along with the ability to identify root causes and implement physical fixes directly in Cadence Innovus and/or Synopsys Fusion Compiler.
You will work closely with Physical Design, Analog/Mixed-Signal, STA, Power Integrity, Reliability, I/O, and CAD teams to drive signoff convergence, establish robust PV methodologies, and achieve first-time-right silicon.
Role Overview
As a Staff/Sr. Staff Physical Verification Engineer at Velaura AI, you will own block-level and full-chip physical verification and signoff for next-generation AI and high-performance computing silicon. You will drive physical verification from block-level implementation through full-chip integration and final tape-out, working on complex SoC designs targeting advanced process technologies.
This is a highly hands-on technical role requiring deep expertise in DRC, LVS, ERC, PERC, antenna, ESD/EOS, and reliability verification, along with the ability to identify root causes and implement physical fixes directly in Cadence Innovus and/or Synopsys Fusion Compiler.
You will work closely with Physical Design, Analog/Mixed-Signal, STA, Power Integrity, Reliability, I/O, and CAD teams to drive signoff convergence, establish robust PV methodologies, and achieve first-time-right silicon.