AMD EPYC Venice Hits TSMC 2nm

May 28 at 2:37 AM6 min read

Visual TL;DR. AI Demands Rise drive AMD EPYC Venice. AMD EPYC Venice on TSMC 2nm Process. TSMC 2nm Process enables First HPC on 2nm. First HPC on 2nm leads to Performance Leaps. Performance Leaps enables Next-Gen Infrastructure. AMD EPYC Venice future Future Arizona Production.

AI Demands Rise: escalating demand for accelerated AI deployments and robust agentic AI workloads
AMD EPYC Venice: 6th Gen AMD EPYC CPUs codenamed 'Venice' begin production ramp
TSMC 2nm Process: manufactured on TSMC’s cutting-edge 2nm process technology
First HPC on 2nm: first high-performance computing products in the industry on TSMC's 2nm
Performance Leaps: promises significant leaps in performance and efficiency for data centers
Next-Gen Infrastructure: powering the next generation of cloud, enterprise, and AI infrastructure
Future Arizona Production: plans to expand manufacturing footprint at TSMC's Arizona facility

Visual TL;DRQuickExplainDeeper

Advanced Micro Devices (AMD) has officially begun the production ramp for its upcoming 6th Gen AMD EPYC™ CPUs, codenamed "Venice." This crucial milestone sees the processors manufactured on TSMC’s cutting-edge 2nm process technology, a collaboration that promises significant leaps in performance and efficiency for data center infrastructure. According to the announcement, this move underscores the escalating demand for accelerated AI deployments and robust agentic AI workloads.

The "Venice" processor is notable as the first high-performance computing (HPC) products in the industry to enter production on TSMC's advanced 2nm process. This development is critical for powering the next generation of cloud, enterprise, and AI infrastructure, where leadership performance and energy efficiency are paramount. AMD plans to expand its advanced manufacturing footprint by also ramping production at TSMC’s Arizona facility in the future.

AI Demands Drive Next-Gen Processors

Dr. Lisa Su, AMD’s Chair and CEO, highlighted the importance of this ramp, stating

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