Chiplets and LLMs Expand Hardware Attack Surface

Chiplets and LLMs revolutionize chip design but dramatically expand the hardware attack surface, necessitating new security paradigms for both systems and EDA flows.

Aug 6 at 8:32 PM6 min read

Diagram illustrating interconnected chiplets on an interposer with an overlay of security threats. — The convergence of chiplet architectures and AI in EDA introduces complex security considerations.

Visual TL;DR. Chiplets & LLMs Emerge leads to Expand Attack Surface. Expand Attack Surface via Heterogeneous Systems. Expand Attack Surface via LLM EDA Pipelines. Heterogeneous Systems requires Isolated Roots of Trust. LLM EDA Pipelines requires Defend EDA Pipelines. Isolated Roots of Trust using Split Manufacturing. Isolated Roots of Trust enables Enhanced Hardware Security. Defend EDA Pipelines contributes to Enhanced Hardware Security.

Chiplets & LLMs Emerge: revolutionizing chip design with modularity and AI-driven automation
Expand Attack Surface: new vulnerabilities across architectural, logical, and physical levels
Heterogeneous Systems: chiplets introduce complex interconnections and diverse component interactions
LLM EDA Pipelines: AI integration into design flows creates novel vectors for exploitation
Isolated Roots of Trust: securing chiplet architectures with physically separated security anchors
Split Manufacturing: leveraging 2.5D active interposers for robust physical isolation
Defend EDA Pipelines: addressing unique threats introduced by LLMs in design automation
Enhanced Hardware Security: a unified security analysis for the dual revolution in chip design

Visual TL;DRQuickExplainDeeper

The semiconductor industry faces a dual revolution: the rise of 2.5D chiplet systems and the integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) flows.

The Proliferation of Vulnerabilities in Heterogeneous Systems

While chiplets promise benefits in yield and modularity, and LLMs enhance design productivity, they fundamentally expand the hardware attack surface across architectural, logical, and physical levels. This convergence introduces new vectors for exploitation that demand a unified security analysis.

Fortifying Chiplet Systems with Isolated Roots of Trust

Securing chiplet architectures necessitates a robust defense strategy, particularly focusing on physically isolated Root of Trust (RoT) implementations. The researchers highlight a powerful approach leveraging 2.5D split manufacturing and active interposers to achieve this necessary isolation.

Defending LLM-Driven EDA Pipelines Against Novel Threats

The integration of LLMs into EDA pipelines presents unique security challenges. This paper identifies native threats inherent to LLM-driven EDA security and reviews existing state-of-the-art defense techniques designed to mitigate these vulnerabilities. The analysis, found on arXiv, underscores the critical need for proactive security measures in these advanced design flows.

Advancing Hardware Security Through AI Collaboration

Looking forward, LLM systems themselves can be instrumental in advancing hardware security for modern systems, including complex chiplet designs. This symbiotic relationship between AI and hardware security is poised to shape the future of secure semiconductor development.

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#AI Research #Semiconductors #Cybersecurity #chiplet security #LLM-driven EDA security #hardware attack surface